Digital ICs IDT clock fanout buffer for JESD204B in LTE basestations
2013/09/24
It is designed to distribute high-quality clock and system synchronisation reference (SYSREF) signals to data converters in GSM, WCDMA and LTE basestation radio cards.
The 8V79S690i supports frequencies such as 614.4 MHz and 1228.8 MHz, addressing the speed requirements of JESD204B analogue-to-digital (ADC) and digital-to-analogue (DAC) data converters, when providing synchronous clock and SYSREF signals in basestations.
According to Christian Kermarrec, vice president and general manager of the Timing and Synchronization Division at IDT, the chip offers “additive phase jitter below 20fs RMS at 1228.8MHz, multiple clock fanout channels, and configurable phase delay for each SYSREF output.”
The two-channel device offers a 1:10 LVPECL/LVDS clock fan-out, and a 1:8 LVDS fan-out for the SYSREF signal. The clock outputs are configurable for both amplitude and phase delay (101 picosecond steps).
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