Memory Products Vertical NAND avoids scaling issues
2013/07/29
“We’re all working on stacked cell NAND,” Glen Hawk, vp of NAND Solutions at Micron, told EW, “the key challenge is going to be cost. We’re not going to do it until it’s cost-effective – and it needs to be capable of dozens of layers before it’s cost-effective.”
“The debate is about how many hundreds of layers you can stack,” added Hawk, “nobody knows how many yet.”
The beauty of stacked NAND is that it removes the need for further scaling. When planar NAND ends, the next generation of NAND – the first generation of 3D vertical NAND – will use a larger geometry process.
“With the vertical NAND stacked cell you can have a more relaxed geometry,” said Hawk, “it’s the first time in my career that we’re selling things that are bigger and cheaper and better all at the same time. Vertical NAND has better reliability and better performance than planar NAND.”
The problem looming for NAND’s future viability was that NAND cells have been running out of electrons as they scale down the micron trail. With a few tens of electrons per cell at sub-20nm, NAND behaviour can become unpredictable. Vertical NAND takes that number back up to hundreds of electrons per cell.
“Vertical NAND is not limited by litho – not limited by fine lines – but by the device physics of the cell,” said Hawk. With quantum effects hitting structures made on 10-20nm processes (where NAND currently is) vertical NAND is the life-saver for NAND technology.
Hawk reckons there will be two more generations of planar NAND and then vertical NAND will come onto the market towards the end of 2015.
“We’re at least two years away from product,” said Hawk, “two years away from it being as cost-effective as planar NAND.”
The development time for vertical NAND has already been about five years. Its significance is that there is now less need to invest in emerging memory technologies like phase change, magnetic memories and memristors.
“There is no emerging technology on the horizon that will replace NAND anytime soon,” said Hawk.
With the NAND industry consolidating around four players – Samsung, Toshiba, Micron and Hynix – there has been some concern that the industry’s capex has been dropping leading to shortages and a longer scaling cycle.
“We’re very mindful that, when we transition from planar to 3D, the process is very different and the equipment is different – it’s a huge cost,” responded Hawk, “so, if there’s only one or two more generations of planar NAND, we don’t want to spend all that money. We expect most of our equipment to last multiple generations.”
Asked why Micron had been one of the last men standing in the memory industry, Hawk replied: “Micron has been excellent at playing the market cycle game – storing cash in the up-times – and not being too fancy. Other people have been investing in non-core activities. “
The manufacturing part of Micron’s NAND joint venture with Intel has transitioned to the point where Intel now has only the output of half a fab – the Utah plant. However the NAND technology part of the Micron-Intel deal is working well.
“We get great results from the technology development with Intel,” said Hawk who spent over 20 years at Intel, “I’ve never seen anything work so well. The engineering culture is very complementary.”
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