Microprocessors Exar samples compression/security co-processor
2013/10/23
Exar XR9200 Series Block Diagram
Exar is sampling a co-processor family for compression and security called XR9200.
The family targets the data analytics, storage, and cloud security markets, including Data Warehouses, Hadoop Clusters, Storage Arrays, Application Delivery Controllers (ADC), WAN Optimization Appliances, and Security Gateways.
The processors provide compression to remove or minimize costly I/O bottlenecks and enable maximum system throughput with minimum latency, while optimizing storage efficiency.
Hardware-accelerated encryption and public key processing enable the secure infrastructure needed to support high transaction throughput and packet-per-second rate required by enterprise, cloud and web-based applications.
The chips offload computationally intensive compression and security algorithms from a host CPU and match the performance of hundreds of enterprise class x86 CPU cores at much lower power and cost.
The family offers:
- 40Gbps processing throughput with simultaneous compression, encryption and hashing
- Compression ratios comparable to Level 9 gzip
- 40,000 operations/second of RSA with 2048 bit keys
- PCI Express 3.0 host interface supporting 64 gigabits/sec of bandwidth with 8 lanes
- 40 gigabit/sec Interlaken interface supports external FPGA connection
- Class of Service to prioritize traffic for critical applications
- Single Root I/O Virtualization (SRIOV) integrates 128 virtual functions to support virtualized I/O
- Support for gzip, zlib, Deflate, and eLZS
- Support for a wide range of symmetric and asymmetric encryption algorithms
- Support for Suite B, multiple wireless algorithms, hardware Random Number Generation, and NIST compliant DRBG
- Security Containment features include a Key Unwrap engine and a Key Encryption Key store with Tamper Zeroization
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